This invention relates to a half-bridge circuit formed of a high side FET and a low side FET which are connected together at a power output node, and more specifically relates to a novel protection circuit for preventing the accidental turn on of the high side and low side FETs at the same time.
Half-bridge circuits are formed of two power MOSFETs or other similar power devices connected in series at a node which defines an output load terminal. The other terminal of the high side FET can be connected to a source of power, for example, the positive terminal of an automobile battery or the like. The other end of the low side FET can be connected to ground. The gate circuits of the high side and low side FETs are then appropriately controlled from an appropriate logic level signal control circuit at some suitable frequency and duty cycle so that the two power FETs turn on and off correctly to provide controlled output power to a load connected to the load terminal. Typical loads can be motor loads, for example, auxiliary motors for controlling various mechanisms in an automobile or the like. Such half bridges may be combined with other half bridges to build up any desired circuit (i.e., an H-bridge or three-phase drive) or may be used by themselves.
If, because of a malfunction in the gate control circuit, both the high side and low side FETs conduct simultaneously, a short circuit is produced from the power source to ground. This short circuit will carry sufficient current that the power FETs are likely to be destroyed. It is, therefore, important to ensure that both the high side and low side FETs do not conduct simultaneously. Great pains are usually taken with the gate control circuits to ensure against this occurrence. However, it is possible that such circuits fail, or that a lead to the gate circuit might be broken, in which case the gate-to-source potential can increase through capacitive coupling from the drain, thereby leading to the accidental turn on of both the high side and low side MOSFETs.